| Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems V Stojanovic, VG Oklobdzija IEEE Journal of solid-state circuits 34 (4), 536-548, 1999 | 892 | 1999 |
| Improved sense-amplifier-based flip-flop: Design and measurements B Nikolic, VG Oklobdzija, V Stojanovic, W Jia, JKS Chiu, MMT Leung IEEE Journal of Solid-State Circuits 35 (6), 876-884, 2000 | 615 | 2000 |
| A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach VG Oklobdzija, D Villeger, SS Liu IEEE Transactions on computers 45 (3), 294-306, 1996 | 496 | 1996 |
| Pass-transistor adiabatic logic using single power-clock supply VG Oklobdzija, D Maksimovic, F Lin IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1997 | 285 | 1997 |
| An algorithmic and novel design of a leading zero detector circuit: Comparison with logic synthesis VG Oklobdzija IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2 (1), 124-128, 1994 | 267 | 1994 |
| Digital system clocking: high-performance and low-power aspects VG Oklobdzija, VM Stojanovic, DM Markovic, NM Nedovic John Wiley & Sons, 2003 | 255 | 2003 |
| Clocked CMOS adiabatic logic with integrated single-phase power-clock supply D Maksimovic, VG Oklobdzija, B Nikolic, KW Current IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8 (4), 460-463, 2000 | 254 | 2000 |
| Optimal circuits for parallel multipliers PF Stelling, CU Martel, VG Oklobdzija, R Ravi IEEE Transactions on Computers 47 (3), 273-285, 1998 | 194 | 1998 |
| Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology VG Oklobdzija, D Villeger IEEE Transactions on Very Large Scale Integration (VLSI) Systems 3 (2), 292-301, 1995 | 193 | 1995 |
| Instruction control mechanism for a computing system with register renaming, map table and queues indicating available registers J Cocke, GF Grohoski, VG Oklobdzija US Patent 4,992,938, 1991 | 188 | 1991 |
| Comparison of high-performance VLSI adders in the energy-delay space VG Oklobdzija, BR Zeydel, HQ Dao, S Mathew, R Krishnamurthy IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (6), 754-758, 2005 | 145 | 2005 |
| Integrated power clock generators for low energy logic D Maksimovic, VG Oklobdzija Proceedings of PESC'95-Power Electronics Specialist Conference 1, 61-67, 1995 | 125 | 1995 |
| Instruction prefetch buffer control VG Oklobdzija, DT Ling US Patent 4,714,994, 1987 | 125 | 1987 |
| Conditional pre-charge techniques for power-efficient dual-edge clocking N Nedovic, M Aleksic, VG Oklobdzija Proceedings of the 2002 international symposium on Low power electronics and …, 2002 | 119 | 2002 |
| A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS SK Hsu, SK Mathew, MA Anders, BR Zeydel, VG Oklobdzija, ... IEEE Journal of solid-state circuits 41 (1), 256-264, 2005 | 118 | 2005 |
| The computer engineering handbook VG Oklobdzija CRC press, 2001 | 116 | 2001 |
| General data-path organization of a MAC unit for VLSI implementation of DSP processors AA Farooqui, VG Oklobdzija 1998 IEEE International Symposium on Circuits and Systems (ISCAS) 2, 260-263, 1998 | 114 | 1998 |
| Dual-edge triggered storage elements and clocking strategy for low-power systems N Nedovic, VG Oklobdzija IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (5), 577-590, 2005 | 112 | 2005 |
| Clocking and clocked storage elements in a multi-gigahertz environment VG Oklobdzija IBM Journal of Research and Development 47 (5.6), 567-583, 2003 | 108 | 2003 |
| Hybrid latch flip-flop with improved power efficiency N Nedovic, VG Oklobdzija Proceedings 13th Symposium on Integrated Circuits and Systems Design (Cat …, 2000 | 102 | 2000 |
