| Configurable circuits featuring dual-threshold-voltage design with three-independent-gate silicon nanowire FETs J Zhang, X Tang, PE Gaillardon, G De Micheli IEEE Transactions on Circuits and Systems I: Regular Papers 61 (10), 2851-2861, 2014 | 95 | 2014 |
| LSOracle: A logic synthesis framework driven by artificial intelligence WL Neto, M Austin, S Temple, L Amaru, X Tang, PE Gaillardon 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-6, 2019 | 72 | 2019 |
| A high-performance low-power near-Vt RRAM-based FPGA X Tang, PE Gaillardon, G De Micheli 2014 International Conference on Field-Programmable Technology (FPT), 207-214, 2014 | 63 | 2014 |
| OpenFPGA: An open-source framework for agile prototyping customizable FPGAs X Tang, E Giacomin, B Chauviere, A Alacchi, PE Gaillardon IEEE Micro 40 (4), 41-48, 2020 | 61 | 2020 |
| OpenFPGA: An opensource framework enabling rapid prototyping of customizable FPGAs X Tang, E Giacomin, A Alacchi, B Chauviere, PE Gaillardon 2019 29th International Conference on Field Programmable Logic and …, 2019 | 60 | 2019 |
| A study on the programming structures for RRAM-based FPGA architectures X Tang, G Kim, PE Gaillardon, G De Micheli IEEE Transactions on Circuits and Systems I: Regular Papers 63 (4), 503-516, 2016 | 56 | 2016 |
| A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells PE Gaillardon, X Tang, G Kim, G De Micheli Transaction on Very Large Scale Integration 23 (10), 2187 - 2197, 2015 | 47 | 2015 |
| Exploring eFPGA-based redaction for IP protection J Bhandari, AKT Moosa, B Tan, C Pilato, G Gore, X Tang, S Temple, ... 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021 | 45 | 2021 |
| A study on switch block patterns for tileable FPGA routing architectures X Tang, E Giacomin, A Alacchi, PE Gaillardon 2019 International Conference on Field-Programmable Technology (ICFPT), 247-250, 2019 | 31 | 2019 |
| Not all fabrics are created equal: Exploring eFPGA parameters for IP redaction J Bhandari, AKT Moosa, B Tan, C Pilato, G Gore, X Tang, S Temple, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31 (10 …, 2023 | 30 | 2023 |
| FPGA-SPICE: A simulation-based architecture evaluation framework for FPGAs X Tang, E Giacomin, G De Micheli, PE Gaillardon IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (3), 637-650, 2018 | 22 | 2018 |
| TSPC flip-flop circuit design with three-independent-gate silicon nanowire FETs X Tang, J Zhang, PE Gaillardon, G De Micheli 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 1660-1663, 2014 | 21 | 2014 |
| ALICE: An automatic design flow for eFPGA redaction CM Tomajoli, L Collini, J Bhandari, AKT Moosa, B Tan, X Tang, ... Proceedings of the 59th ACM/IEEE Design Automation Conference, 781-786, 2022 | 20 | 2022 |
| Circuit designs of high-performance and low-power RRAM-based multiplexers based on 4T (ransistor) 1R (RAM) programming structure X Tang, E Giacomin, G De Micheli, PE Gaillardon IEEE Transactions on Circuits and Systems I: Regular Papers 64 (5), 1173-1186, 2016 | 20 | 2016 |
| Post-P&R performance and power analysis for RRAM-based FPGAs X Tang, E Giacomin, G De Micheli, PE Gaillardon IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8 (3 …, 2018 | 17 | 2018 |
| A high-performance FPGA architecture using one-level RRAM-based multiplexers X Tang, G De Micheli, PE Gaillardon IEEE Transactions on Emerging Topics in Computing 5 (2), 210-222, 2016 | 17 | 2016 |
| A ultra-low-power FPGA based on monolithically integrated RRAMs PE Gaillardon, X Tang, J Sandrini, M Thammasack, SR Omam, ... 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015 | 17 | 2015 |
| FPGA-SPICE: A simulation-based power estimation framework for FPGAs X Tang, PE Gaillardon, G De Micheli 2015 33rd IEEE International Conference on Computer Design (ICCD), 696-703, 2015 | 16 | 2015 |
| Accurate power analysis for near-Vt RRAM-based FPGA X Tang, PE Gaillardon, G De Micheli 2015 25th International Conference on Field Programmable Logic and …, 2015 | 13 | 2015 |
| Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise H Xu, VF Pavlidis, X Tang, W Burleson, G De Micheli IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (12 …, 2013 | 13 | 2013 |
Pierre - Emmanuel GAILLARDONProfessor, University of UtahVerified email at utah.edu
