Nithin George

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Paolo IenneProfessor, EPFLVerified email at epfl.ch
NOVO DavidLIRMM,University of Montpellier, and CNRSVerified email at lirmm.fr
Martin OderskyEPFLVerified email at epfl.ch
Tiark RompfPurdue UniversityVerified email at purdue.edu
Kunle OlukotunCadence Design Systems Professor of Computer Science, Stanford UniversityVerified email at stanford.edu
Kizheppatt VipinAssistant Professor, BITS Pilani, KK Birla Goa CampusVerified email at goa.bits-pilani.ac.in
Mikhail AsiaticiComputer Architect, AMDVerified email at amd.com
Suhaib FahmyAssociate Professor, King Abdullah University of Science and Technology (KAUST)Verified email at kaust.edu.sa
Gabriel FalcaoProfessor of Electrical and Computer Engineering, FCTUC, University of Coimbra, IT, PortugalVerified email at deec.uc.pt
Joao AndradeApplications Engineer, Synopsys Inc.Verified email at synopsys.com
Kimon KarrasAnalog DevicesVerified email at f-in.co.uk
Vitor SilvaProfessor de Engenharia Electrotécnica e de Computadores, Universidade de CoimbraVerified email at co.it.pt
Arvind K. SujeethStanford UniversityVerified email at stanford.edu
Muhsen OwaidaMagic LeapVerified email at magicleap.com
Lana JosipovićETH ZurichVerified email at ethz.ch
Philip BriskUniversity of California, RiversideVerified email at cs.ucr.edu
yehdhih ould mohammed moctarUniversity of California RiversideVerified email at cs.ucr.edu
Guy LemieuxFaculty of Applied Science, University of British Columbia, V6T 1Z4Verified email at ece.ubc.ca
Hadi Parandeh-AfsharQualcomm Technologies, Inc.Verified email at qti.qualcomm.com

Nithin George

Intel Corporation (previously, École Polytechnique Fédérale de Lausanne)

Verified email at intel.com

High-level synthesis domain-specific languages reconfigurable computing FPGA CGRA


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Hardware system synthesis from domain-specific languages N George, HJ Lee, D Novo, T Rompf, KJ Brown, AK Sujeeth, M Odersky, ... 2014 24th International Conference on Field Programmable Logic and …, 2014	91	2014
Virtualized execution runtime for FPGA accelerators in the cloud M Asiatici, N George, K Vipin, SA Fahmy, P Ienne Ieee Access 5, 1900-1910, 2017	86	2017
SuSy: A programming model for productive construction of high-performance systolic arrays on FPGAs YH Lai, H Rong, S Zheng, W Zhang, X Cui, Y Jia, J Wang, B Sullivan, ... Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020	54	2020
Design space exploration of LDPC decoders using high-level synthesis J Andrade, N George, K Karras, D Novo, F Pratas, L Sousa, P Ienne, ... IEEE Access 5, 14600-14615, 2017	30	2017
Making domain-specific hardware synthesis tools cost-efficient N George, D Novo, T Rompf, M Odersky, P Ienne 2013 International Conference on Field-Programmable Technology (FPT), 120-127, 2013	29	2013
Designing a virtual runtime for FPGA accelerators in the cloud M Asiatici, N George, K Vipin, SA Fahmy, P Ienne 2016 26th international conference on field programmable logic and …, 2016	17	2016
From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis J Andrade, N George, K Karras, D Novo, V Silva, P Ienne, G Falcão 2015 25th International Conference on Field Programmable Logic and …, 2015	14	2015
Automatic support for multi-module parallelism from computational patterns N George, HJ Lee, D Novo, M Owaida, D Andrews, K Olukotun, P Ienne 2015 25th International Conference on Field Programmable Logic and …, 2015	12	2015
Enriching C-based High-Level Synthesis with parallel pattern templates L Josipovic, N George, P Ienne 2016 International Conference on Field-Programmable Technology (FPT), 177-180, 2016	11	2016
Fast design space exploration using vivado HLS: Non-binary LDPC decoders J Andrade, N George, K Karras, D Novo, V Silva, P Ienne, G Falcao 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom …, 2015	10	2015
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs YOM Moctar, N George, H Parandeh-Afshar, P Ienne, GGF Lemieux, ... Proceedings of the ACM/SIGDA international symposium on Field Programmable …, 2012	10	2012
CodePin: An Instrumentation-Based Debug Tool of SYCLomatic A Huang, Z Wang, W Ni, S Chen, N George Proceedings of the 12th International Workshop on OpenCL and SYCL, 1-2, 2024		2024
SuSy YH Lai, H Rong, S Zheng, W Zhang, X Cui, Y Jia, J Wang, B Sullivan, ... Proceedings of the 39th International Conference on Computer-Aided Design, 2020		2020
FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages N George EPFL, 2016		2016
LAP M Asiatici, K Atasu, P Athanasopoulos, AG Bayrak, AJ Becker, R Beuchat, ...
Heterogeneity and Reconfigurability as Key Enablers for Energy Efficient Computing N George

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