William Hasenplaugh
William Hasenplaugh
D. E. Shaw Research
Verified email at
Cited by
Cited by
Adaptive insertion policies for managing shared caches
A Jaleel, W Hasenplaugh, M Qureshi, J Sebot, S Steely Jr, J Emer
Proceedings of the 17th international conference on Parallel architectures …, 2008
SHiP: Signature-based hit predictor for high performance caching
CJ Wu, A Jaleel, W Hasenplaugh, M Martonosi, SC Steely Jr, J Emer
Proceedings of the 44th Annual IEEE/ACM International Symposium on …, 2011
Anton 3: twenty microseconds of molecular dynamics simulation before lunch
DE Shaw, PJ Adams, A Azaria, JA Bank, B Batson, A Bell, M Bergdorf, ...
Proceedings of the International Conference for High Performance Computing …, 2021
Ordering heuristics for parallel graph coloring
W Hasenplaugh, T Kaler, TB Schardl, CE Leiserson
Proceedings of the 26th ACM symposium on Parallelism in algorithms and …, 2014
Variable precision floating point multiply-add circuit
H Kaul, MA Anders, SK Mathew, RK Krishnamurthy, WC Hasenplaugh, ...
US Patent 9,104,474, 2015
Dynamic quality of service (QoS) for a shared cache
WC Hasenplaugh, L Zhao, R Iyer, R Illikkal, S Makineni, D Newell, ...
US Patent 7,725,657, 2010
Fast modular reduction
W Hasenplaugh, G Gaubatz, V Gopal
18th IEEE Symposium on Computer Arithmetic (ARITH'07), 225-229, 2007
Determining message residue using a set of polynomials
WC Hasenplaugh, BA Burres, G Gaubatz
US Patent 7,827,471, 2010
Executing dynamic data-graph computations deterministically using chromatic scheduling
T Kaler, W Hasenplaugh, TB Schardl, CE Leiserson
ACM Transactions on Parallel Computing (TOPC) 3 (1), 1-31, 2016
Low energy consumption mantissa multiplication for floating point multiply-add operations
WC Hasenplaugh, KE Fleming, T Fossum, SC Steely Jr
US Patent 10,402,168, 2019
Cache spill management techniques using cache spill prediction
SC Steely Jr, WC Hasenplaugh, A Jaleel, GZ Chrysos
US Patent 8,407,421, 2013
Multiaperture imaging
PM Shankar, WC Hasenplaugh, RL Morrison, RA Stack, MA Neifeld
Applied optics 45 (13), 2871-2883, 2006
System and method for cryptography processing units and multiplier
WK Feghali, WC Hasenplaugh, GM Wolrich, DR Cutter, V Gopal, ...
US Patent 7,725,624, 2010
Multiplying two numbers
WC Hasenplaugh, G Gaubatz, V Gopal, MM Bace
US Patent 7,930,337, 2011
The gradient-based cache partitioning algorithm
W Hasenplaugh, PS Ahuja, A Jaleel, S Steely Jr, J Emer
ACM Transactions on Architecture and Code Optimization (TACO) 8 (4), 1-21, 2012
Cryptographic system, method and multiplier
WK Feghali, WC Hasenplaugh, GM Wolrich, DR Cutter, V Gopal, ...
US Patent 8,073,892, 2011
Hardware accelerator
GM Wolrich, W Hasenplaugh, W Feghali, D Cutter, V Gopal, G Gaubatz
US Patent 8,020,142, 2011
A synergetic approach to throughput computing on x86-based multicore desktops
CK Luk, R Newton, W Hasenplaugh, M Hampton, G Lowney
IEEE software 28 (1), 39, 2011
Cryptographic system component
W Feghali, W Hasenplaugh, G Wolrich, D Cutter, V Gopal
US Patent App. 11/323,329, 2007
Hardware apparatuses and methods to control cache line coherency
SC Steely Jr, SS Sury, WC Hasenplaugh
US Patent 9,934,146, 2018
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