| MAERI: Enabling Flexible Dataflow Mapping over DNN Accelerators via Programmable Interconnects H Kwon, A Samajdar, T Krishna Sysml, 2018 | 536* | 2018 |
| SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training E Qin, A Samajdar, H Kwon, V Nadella, S Srinivasan, D Das, B Kaul, ... International Symposium on High Performance Computer Architecture, 2020 | 465 | 2020 |
| SCALE-Sim: Systolic CNN Accelerator Simulator A Samajdar, Y Zhu, P Whatmough, M Mattina, T Krishna arXiv preprint arXiv:1811.02883, 2018 | 316 | 2018 |
| A Systematic Methodology for Characterizing Scalability of DNN Accelerators using SCALE-Sim A Samajdar, JM Joseph, Y Zhu, P Whatmough, M Mattina, T Krishna 2020 IEEE International Symposium on Performance Analysis of Systems and …, 2020 | 194 | 2020 |
| Euphrates: Algorithm-SoC Co-Design for Low-Power Mobile Continuous Vision Y Zhu, A Samajdar, M Mattina, P Whatmough International Symposium on Computer Architecture, 2018 | 110 | 2018 |
| Scale-sim: Systolic CNN accelerator A Samajdar, Y Zhu, PN Whatmough, M Mattina, T Krishna CoRR, 2018 | 89 | 2018 |
| Rethinking NoCs for spatial neural network accelerators H Kwon, A Samajdar, T Krishna Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on …, 2017 | 86 | 2017 |
| Scaling the Cascades: Interconnect-aware FPGA implementation of Machine Learning problems A Samajdar, T Garg, T Krishna, N Kapre 29th International Conference on Field Programmable Logic and Applications (FPL), 2019 | 26 | 2019 |
| GeneSys: Enabling Continuous Learning through Neural Network Evolution in Hardware A Samajdar, P Mannan, K Garg, T Krishna The 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2018 | 26 | 2018 |
| Data orchestration in deep learning accelerators T Krishna, H Kwon, A Parashar, M Pellauer, A Samajdar Morgan & Claypool Publishers 15, 1-164, 2020 | 21 | 2020 |
| RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU TK Geonhwa Jeong, Eric Qin, Ananda Samajdar, Christopher J. Hughes ... 58th Annual Design Automation Conference (DAC), 2021 | 19* | 2021 |
| A communication-centric approach for designing flexible DNN accelerators H Kwon, A Samajdar, T Krishna IEEE Micro 38 (6), 25-35, 2018 | 14 | 2018 |
| Self adaptive reconfigurable arrays (SARA) learning flexible GEMM accelerator configuration and mapping-space using ML A Samajdar, E Qin, M Pellauer, T Krishna Proceedings of the 59th ACM/IEEE Design Automation Conference, 583-588, 2022 | 12 | 2022 |
| Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators J Moritz Joseph, A Samajdar, L Zhu, R Leupers, S Kyu Lim, T Pionteck, ... International Symposium on Quality Electronic Design, 2021 | 12* | 2021 |
| Scale-sim: Systolic cnn accelerator simulator. arXiv 2018 A Samajdar, Y Zhu, P Whatmough, M Mattina, T Krishna arXiv preprint arXiv:1811.02883, 0 | 10 | |
| AIRCHITECT: Learning custom architecture design and mapping space A Samajdar, JM Joseph, M Denton, T Krishna arXiv preprint arXiv:2108.08295, 2021 | 6 | 2021 |
| Self-adaptive reconfigurable arrays (sara): Using ml to assist scaling gemm acceleration A Samajdar, M Pellauer, T Krishna arXiv preprint arXiv:2101.04799, 2021 | 5 | 2021 |
| Towards cognitive ai systems: Workload and characterization of neuro-symbolic ai Z Wan, CK Liu, H Yang, R Raj, C Li, H You, Y Fu, C Wan, A Samajdar, ... 2024 IEEE International Symposium on Performance Analysis of Systems and …, 2024 | 2 | 2024 |
| AIrchitect: Automating Hardware Architecture and Mapping Optimization A Samajdar, JM Joseph, T Krishna 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023 | 2 | 2023 |
| Towards Efficient Neuro-Symbolic AI: From Workload Characterization to Hardware Architecture Z Wan, CK Liu, H Yang, R Raj, C Li, H You, Y Fu, C Wan, S Li, Y Kim, ... IEEE Transactions on Circuits and Systems for Artificial Intelligence, 2024 | 1 | 2024 |
Tushar KrishnaAssociate Professor, Georgia TechVerified email at ece.gatech.edu
