| Low-cost online convolution checksum checker D Filippas, N Margomenos, N Mitianoudis, C Nicopoulos, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (2), 201-212, 2021 | 22 | 2021 |
| Reduced-Precision Floating-Point Arithmetic in Systolic Arrays with Skewed Pipelines D Filippas, C Peltekis, G Dimitrakopoulos, C Nicopoulos 2023 IEEE 5th International Conference on Artificial Intelligence Circuits …, 2023 | 8 | 2023 |
| Synthesis of Approximate Parallel-Prefix Adders A Stefanidis, I Zoumpoulidou, D Filippas, G Dimitrakopoulos, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023 | 7 | 2023 |
| ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining C Peltekis, D Filippas, G Dimitrakopoulos, C Nicopoulos, ... 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023 | 7 | 2023 |
| FusedGCN: A systolic three-matrix multiplication architecture for graph convolutional networks C Peltekis, D Filippas, C Nicopoulos, G Dimitrakopoulos 2022 IEEE 33rd International Conference on Application-specific Systems …, 2022 | 7 | 2022 |
| Streaming dilated convolution engine D Filippas, C Nicopoulos, G Dimitrakopoulos IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31 (3), 401-405, 2023 | 6 | 2023 |
| Templatized fused vector floating-point dot product for high-level synthesis D Filippas, C Nicopoulos, G Dimitrakopoulos Journal of Low Power Electronics and Applications 12 (4), 56, 2022 | 5 | 2022 |
| Low-power data streaming in systolic arrays with bus-invert coding and zero-value clock gating C Peltekis, D Filippas, G Dimitrakopoulos, C Nicopoulos 2023 12th International Conference on Modern Circuits and Systems …, 2023 | 2 | 2023 |
| Exploiting data encoding and reordering for low-power streaming in systolic arrays C Peltekis, D Filippas, G Dimitrakopoulos, C Nicopoulos Microprocessors and Microsystems 102, 104938, 2023 | 1 | 2023 |
| LeapConv: An Energy-Efficient Streaming Convolution Engine with Reconfigurable Stride D Filippas, C Nicopoulos, G Dimitrakopoulos 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 200-205, 2022 | 1 | 2022 |
| Floating-Point Multiply-Add with Approximate Normalization for Low-Cost Matrix Engines K Alexandridis, C Peltekis, D Filippas, G Dimitrakopoulos arXiv preprint arXiv:2408.11997, 2024 | | 2024 |
| A High-Level Synthesis Library for Synthesizing Efficient and Functional-Safe CNN Dataflow Accelerators D Filippas, C Peltekis, V Titopoulos, I Kansizoglou, G Sirakoulis, ... IEEE Access, 2024 | | 2024 |
| Error Checking for Sparse Systolic Tensor Arrays C Peltekis, D Filippas, G Dimitrakopoulos arXiv preprint arXiv:2402.10850, 2024 | | 2024 |
| The Case for Asymmetric Systolic Array Floorplanning C Peltekis, D Filippas, G Dimitrakopoulos, C Nicopoulos arXiv preprint arXiv:2309.02969, 2023 | | 2023 |
| Hardware accelerators for data clustering using High Level Synthesis D Filippas | | 2021 |
Giorgos DimitrakopoulosProfessor, ECE, Democritus University of ThraceVerified email at ee.duth.gr
