| A top-down design methodology for ultrahigh-performance hashing cores H Michail, A Kakarountas, A Milidonis, C Goutis IEEE Transactions on Dependable and Secure Computing 6 (4), 255-268, 2008 | 55 | 2008 |
| Efficient implementation of the keyed-hash message authentication code (HMAC) using the SHA-1 hash function HE Michail, AP Kakarountas, A Milidonis, CE Goutis Proceedings of the 2004 11th IEEE International Conference on Electronics …, 2004 | 54 | 2004 |
| High-speed FPGA implementation of secure hash algorithm for IPSec and VPN applications AP Kakarountas, H Michail, A Milidonis, CE Goutis, G Theodoridis The Journal of Supercomputing 37, 179-195, 2006 | 30 | 2006 |
| Novel high throughput implementation of SHA-256 hash function through pre-computation technique H Michail, A Milidonis, A Kakarountas, C Goutis 2005 12th IEEE International Conference on Electronics, Circuits and Systems …, 2005 | 22 | 2005 |
| A partitioning methodology for accelerating applications in hybrid reconfigurable platforms MD Galanis, A Milidonis, G Theodoridis, D Soudris, CE Goutis Design, Automation and Test in Europe, 247-252, 2005 | 14 | 2005 |
| Autonomous drone charging stations: A survey C Mourgelas, S Kokkinos, A Milidonis, I Voyiatzis Proceedings of the 24th Pan-Hellenic Conference on Informatics, 233-236, 2020 | 13 | 2020 |
| A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000 G Dimitroulakos, MD Galanis, A Milidonis, CE Goutis Integration 39 (1), 1-11, 2005 | 13 | 2005 |
| A low power design for sbox cryptographic primitive of advanced encryption standard for mobile end-users GN Selimis, AP Kakarountas, AP Fournaris, A Milidonis, O Koufopavlou Journal of Low Power Electronics 3 (3), 327-336, 2007 | 9 | 2007 |
| A high-throughput and memory efficient 2D discrete wavelet transform hardware architecture for JPEG2000 standard G Dimitroulakos, MD Galanis, A Milidonis, CE Goutis 2005 IEEE International Symposium on Circuits and Systems, 472-475, 2005 | 6 | 2005 |
| An effective two-pattern test generator for Arithmetic BIST I Voyiatzis, C Efstathiou, H Antonopoulou, A Milidonis Computers & Electrical Engineering 39 (2), 398-409, 2013 | 5 | 2013 |
| Exploration and enhancement of P1619-based crypto-cores for efficient performance E Hatzidimitriou, AP Kakarountas, A Milidonis 2011 IEEE International Conference on Consumer Electronics (ICCE), 361-362, 2011 | 5 | 2011 |
| A high-speed and area efficient hardware implementation of AES-128 encryption standard A Brokalakis, H Michail, A Kakarountas, E Fotopoulou, A Milidonis, ... Proc. of the 5th WSEAS Int. Conf. on Multimedia, Internet and Video Technologies, 2005 | 5 | 2005 |
| A survey on throughput-efficient architectures for IEEE P1619 for shared storage media AP Kakarountas, E Hatzidimitriou, A Milidonis 2011 IEEE Symposium on Computers and Communications (ISCC), 758-763, 2011 | 4 | 2011 |
| Automated framework for partitioning DSP applications in hybrid reconfigurable platforms MD Galanis, A Milidonis, G Theodoridis, D Soudris, CE Goutis Microprocessors and Microsystems 31 (1), 1-14, 2007 | 4 | 2007 |
| Temporal and system level modifications for high speed VLSI implementations of cryptographic core HE Michail, AP Kakarountas, AS Milidonis, GA Panagiotakopoulos, ... 2006 13th IEEE International Conference on Electronics, Circuits and Systems …, 2006 | 4 | 2006 |
| A methodology for partitioning DSP applications in hybrid reconfigurable systems MD Galanis, A Milidonis, G Theodoridis, D Soudris, CE Goutis 2005 IEEE International Symposium on Circuits and Systems, 1206-1209, 2005 | 4 | 2005 |
| A method for partitioning applications in hybrid reconfigurable architectures MD Galanis, A Milidonis, G Theodoridis, D Soudris, CE Goutis Design Automation for Embedded Systems 10, 27-47, 2005 | 4 | 2005 |
| Arithmetic module-based built-in self test architecture for two-pattern testing I Voyiatzis, C Efstathiou, H Antonopoulou, A Milidonis IET computers & digital techniques 6 (4), 195-204, 2012 | 3 | 2012 |
| Decoupled Processors Architecture for Accelerating Data Intensive Applications using Scratch-Pad Memory Hierarchy A Milidonis, N Alachiotis, V Porpodas, H Michail, G Panagiotakopoulos, ... Journal of Signal Processing Systems 59, 281-296, 2010 | 3 | 2010 |
| A decoupled architecture of processors with scratch-pad memory hierarchy A Milidonis, N Alachiotis, V Porpodas, H Michail, AP Kakarountas, ... 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 3 | 2007 |
