| Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU VW Lee, C Kim, J Chhugani, M Deisher, D Kim, AD Nguyen, N Satish, ... Proceedings of the 37th annual international symposium on Computer …, 2010 | 1175 | 2010 |
| An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches C Kim, D Burger, SW Keckler Proceedings of the 10th international conference on Architectural support …, 2002 | 1055 | 2002 |
| Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture K Sankaralingam, R Nagarajan, H Liu, C Kim, J Huh, D Burger, ... Proceedings of the 30th annual international symposium on Computer …, 2003 | 745 | 2003 |
| A NUCA substrate for flexible CMP cache sharing J Huh, C Kim, H Shafi, L Zhang, D Burger, SW Keckler ACM International Conference on Supercomputing 25th Anniversary Volume, 380-389, 2005 | 488 | 2005 |
| FAST: fast architecture sensitive tree search on modern CPUs and GPUs C Kim, J Chhugani, N Satish, E Sedlar, AD Nguyen, T Kaldewey, VW Lee, ... Proceedings of the 2010 ACM SIGMOD International Conference on Management of …, 2010 | 424 | 2010 |
| Sort vs. hash revisited: Fast join implementation on modern multi-core CPUs C Kim, T Kaldewey, VW Lee, E Sedlar, AD Nguyen, N Satish, J Chhugani, ... Proceedings of the VLDB Endowment 2 (2), 1378-1389, 2009 | 418 | 2009 |
| Clearpath: highly parallel collision avoidance for multi-agent simulation SJ Guy, J Chhugani, C Kim, N Satish, M Lin, D Manocha, P Dubey Proceedings of the 2009 ACM SIGGRAPH/Eurographics Symposium on Computer …, 2009 | 418 | 2009 |
| 3.5-D blocking optimization for stencil computations on modern CPUs and GPUs A Nguyen, N Satish, J Chhugani, C Kim, P Dubey SC'10: Proceedings of the 2010 ACM/IEEE International Conference for High …, 2010 | 388 | 2010 |
| Fast sort on CPUs and GPUs: a case for bandwidth oblivious SIMD sort N Satish, C Kim, J Chhugani, AD Nguyen, VW Lee, D Kim, P Dubey Proceedings of the 2010 ACM SIGMOD International Conference on Management of …, 2010 | 304 | 2010 |
| Composable lightweight processors C Kim, S Sethumadhavan, MS Govindan, N Ranganathan, D Gulati, ... 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO …, 2007 | 259 | 2007 |
| Second life and the new generation of virtual worlds S Kumar, J Chhugani, C Kim, D Kim, A Nguyen, P Dubey, C Bienia, Y Kim Computer 41 (9), 46-53, 2008 | 256 | 2008 |
| Implementation and evaluation of on-chip network architectures P Gratz, C Kim, R McDonald, SW Keckler, D Burger 2006 International Conference on Computer Design, 477-484, 2006 | 256 | 2006 |
| Distributed microarchitectural protocols in the TRIPS prototype processor K Sankaralingam, R Nagarajan, R McDonald, R Desikan, S Drolia, ... 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture …, 2006 | 231 | 2006 |
| Fast updates on read-optimized databases using multi-core CPUs J Krueger, C Kim, M Grund, N Satish, D Schwalb, J Chhugani, H Plattner, ... arXiv preprint arXiv:1109.6885, 2011 | 191 | 2011 |
| On-chip interconnection networks of the TRIPS chip P Gratz, C Kim, K Sankaralingam, H Hanson, P Shivakumar, SW Keckler, ... IEEE Micro 27 (5), 41-50, 2007 | 149 | 2007 |
| Can traditional programming bridge the ninja performance gap for parallel computing applications? N Satish, C Kim, J Chhugani, H Saito, R Krishnaiyer, M Smelyanskiy, ... ACM SIGARCH Computer Architecture News 40 (3), 440-451, 2012 | 146 | 2012 |
| PALM: Parallel architecture-friendly latch-free modifications to B+ trees on many-core processors J Sewall, J Chhugani, C Kim, N Satish, P Dubey Proceedings of the VLDB Endowment 4 (11), 795-806, 2011 | 143 | 2011 |
| Nonuniform cache architectures for wire-delay dominated on-chip caches C Kim, D Burger, SW Keckler IEEE Micro 23 (6), 99-107, 2003 | 143 | 2003 |
| Trips: A polymorphous architecture for exploiting ilp, tlp, and dlp K Sankaralingam, R Nagarajan, H Liu, C Kim, J Huh, N Ranganathan, ... ACM Transactions on Architecture and Code Optimization (TACO) 1 (1), 62-93, 2004 | 122 | 2004 |
| Fast and efficient graph traversal algorithm for CPUs: Maximizing single-node efficiency J Chhugani, N Satish, C Kim, J Sewall, P Dubey 2012 IEEE 26th International Parallel and Distributed Processing Symposium …, 2012 | 120 | 2012 |
