Introduction of local memory elements in instruction set extensions P Biswas, V Choudhary, K Atasu, L Pozzi, P Ienne, N Dutt Proceedings of the 41st annual Design Automation Conference, 729-734, 2004 | 93 | 2004 |
ISEGEN: Generation of high-quality instruction set extensions by iterative improvement P Biswas, S Banerjee, N Dutt, L Pozzi, P Ienne Design, Automation and Test in Europe, 1246-1251, 2005 | 74 | 2005 |
An efficient compiler technique for code size reduction using reduced bit-width ISAs A Halambi, A Shrivastava, P Biswas, N Dutt, A Nicolau Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002 | 68 | 2002 |
Automatic identification of application-specific functional units with architecturally visible storage P Biswas, N Dutt, P Ienne, L Pozzi Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006 | 61* | 2006 |
Performance and energy benefits of instruction set extensions in an FPGA soft core P Biswas, S Banerjee, N Dutt, P Ienne, L Pozzi 19th International Conference on VLSI Design held jointly with 5th …, 2006 | 48 | 2006 |
ISEGEN: An iterative improvement-based ISE generation technique for fast customization of processors P Biswas, S Banerjee, ND Dutt, L Pozzi, P Ienne IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14 (7), 754-762, 2006 | 42 | 2006 |
Introduction of architecturally visible storage in instruction set extensions P Biswas, ND Dutt, L Pozzi, P Ienne IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007 | 37 | 2007 |
Model level power consumption optimization in hardware description generation P Biswas, Z Zhao, W Chen, Y Gu US Patent 9,355,000, 2016 | 24 | 2016 |
Compilation framework for code size reduction using reduced bit-width ISAs (rISAs) A Shrivastava, P Biswas, A Halambi, N Dutt, A Nicolau ACM Transactions on Design Automation of Electronic Systems (TODAES) 11 (1 …, 2006 | 22 | 2006 |
A design space exploration framework for reduced bit-width instruction set architecture (rISA) design A Halambi, A Shrivastava, P Biswas, N Dutt, A Nicolau Proceedings of the 15th international symposium on System Synthesis, 120-125, 2002 | 18 | 2002 |
Identification of resource sharing patterns through isomorphic subtree enumeration G Venkataramani, P Biswas US Patent 8,352,505, 2013 | 17 | 2013 |
Technique for automatically assigning placement for pipeline registers within code generated from a program specification P Biswas, V Raghavan, Z Zhao US Patent 8,402,449, 2013 | 16 | 2013 |
Code size reduction in heterogeneous-connectivity-based DSPs using instruction set extensions P Biswas, ND Dutt IEEE Transactions on Computers 54 (10), 1216-1226, 2005 | 12 | 2005 |
Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions P Biswas, N Dutt Proceedings of the 2003 international conference on Compilers, architecture …, 2003 | 12 | 2003 |
Automatic generation of an optimized arrangement for a model and optimized code based on the model Y Zhang, B Cockerham, X Lin, P Biswas US Patent 9,098,292, 2015 | 9 | 2015 |
Fast automated generation of high-quality instruction set extensions for processor customization P Biswas, S Banerjee, N Dutt, L Pozzi, P Ienne 3rd Workshop on Application Specific Processors, 2004 | 8 | 2004 |
Greedy and heuristic-based algorithms for synthesis of complex instructions in heterogeneous-connectivity-based DSPs P Biswas, N Dutt School Inf. Comput. Sci., Univ. California, Irvine, Tech. Rep, 03-16, 2003 | 7 | 2003 |
A framework for GUI-Driven design space exploration of a MIPS4K-like processor S Pasricha, P Biswas, P Mishra, A Shrivastava, A Mandal, N Dutt, ... Center for Embedded Computer Systems, 2003 | 7 | 2003 |
Automatic generation of domain-aware phase ordering for effective optimization of code for a model Y Zhang, P Biswas, X Lin US Patent 9,268,537, 2016 | 5 | 2016 |
Comprehensive isomorphic subtree enumeration P Biswas, G Venkataramani Proceedings of the 2008 international conference on Compilers, architectures …, 2008 | 5 | 2008 |