Dopant distribution in the recrystallization transient at the maximum melt depth induced by laser annealing KK Ong, KL Pey, PS Lee, ATS Wee, XC Wang, YF Chong Applied physics letters 89 (17), 2006 | 298 | 2006 |
Method to control source/drain stressor profiles for stress engineering YF Chong, Z Luo, JR Holt US Patent 8,017,487, 2011 | 131 | 2011 |
Formation of raised source/drain structures in NFET with embedded SiGe in PFET YF Chong, Z Luo, JC Kim, JR Holt US Patent 7,718,500, 2010 | 104 | 2010 |
Annealing of ultrashallow junction by 248 nm excimer laser and rapid thermal processing with different preamorphization depths YF Chong, KL Pey, ATS Wee, A See, L Chan, YF Lu, WD Song, LH Chua Applied Physics Letters 76 (22), 3197-3199, 2000 | 99 | 2000 |
Method for engineering hybrid orientation/material semiconductor substrate Y Chong, L Hsia, C Ang US Patent App. 10/990,180, 2006 | 79 | 2006 |
Method and structure to prevent silicide strapping of source/drain to body in semiconductor devices with source/drain stressor YF Chong, BJ Greene US Patent 7,405,131, 2008 | 71 | 2008 |
Semiconductor system using germanium condensation SS Tan, YF Chong, LW Teo US Patent 8,211,761, 2012 | 65 | 2012 |
Formation of silicided shallow junctions using implant through metal technology and laser annealing process YF Chong, KL Pey, A See US Patent 6,624,489, 2003 | 59* | 2003 |
Integrated circuit system employing a condensation process LW Teo, YF Chong, EKB Quek, A Chan US Patent 7,692,213, 2010 | 52 | 2010 |
Embedded stressor structure and process YF Chong, Z Luo, JC Kim, BJ Greene, K Rim US Patent 7,939,413, 2011 | 51 | 2011 |
Strained channel transistor and method of fabrication thereof YF Chong, Z Luo, J Holt US Patent 7,772,071, 2010 | 48 | 2010 |
Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same JP Han, A Gutmann, R Knoefler, J Yan, C Stapelmann, J Lian, YF Chong US Patent 7,800,182, 2010 | 40 | 2010 |
Activating source and drain junctions and extensions using a single laser anneal YF Chong, KL Pey, A See US Patent 6,391,731, 2002 | 39 | 2002 |
Laser activation of implanted contact plug for memory bitline fabrication YF Chong, DK Sohn, LC Hsia US Patent 7,256,112, 2007 | 36 | 2007 |
Network access coordination of load control devices JT Neyhart US Patent 10,050,444, 2018 | 34* | 2018 |
Split gate embedded memory technology and method of manufacturing thereof D Shum, FH Lee, YFA Chong US Patent 9,257,554, 2016 | 32 | 2016 |
Method to engineer etch profiles in Si substrate for advanced semiconductor devices YF Chong, BJ Greene, S Panda, N Rovedo US Patent 7,442,618, 2008 | 32 | 2008 |
An investigation on the plasma treatment of integrated circuit bond pads YF Chong, R Gopalakrishnan, CF Tsang, G Sarkar, S Lim, S Tatti Microelectronics reliability 40 (7), 1199-1206, 2000 | 32 | 2000 |
Formation of silicided ultra-shallow junctions using implant through metal technology and laser annealing process YF Chong, KL Pey, A See US Patent 6,365,446, 2002 | 31 | 2002 |
Design of high performance PFETs with strained Si channel and laser anneal Z Luo, YF Chong, J Kim, N Rovedo, B Greene, S Panda, T Sato, J Holt, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005 | 30 | 2005 |