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Dimitris Nikolos
Dimitris Nikolos
Professor, Computer Engineering & Informatics Dept, University of Patras
Verified email at ceid.upatras.gr - Homepage
Title
Cited by
Cited by
Year
High-speed parallel-prefix VLSI Ling adders
G Dimitrakopoulos, D Nikolos
IEEE Transactions on Computers 54 (2), 225-231, 2005
2122005
High-speed parallel-prefix module 2/sup n/-1 adders
L Kalampoukas, D Nikolos, C Efstathiou, HT Vergos, J Kalamatianos
IEEE Transactions on Computers 49 (7), 673-680, 2000
2032000
Diminished-one modulo 2/sup n/+ 1 adder design
HT Vergos, C Efstathiou, D Nikolos
IEEE Transactions on Computers 51 (12), 1389-1399, 2002
1982002
Optimal selective Huffman coding for test-data compression
X Kavousianos, E Kalligeros, D Nikolos
IEEE transactions on computers 56 (8), 1146-1152, 2007
1602007
Fast parallel-prefix modulo 2/sup n/+ 1 adders
C Efstathiou, HT Vergos, D Nikolos
IEEE Transactions on Computers 53 (9), 1211-1216, 2004
1282004
Efficient diminished-1 modulo 2/sup n/+ 1 multipliers
C Efstathiou, HT Vergos, G Dimitrakopoulos, D Nikolos
IEEE Transactions on Computers 54 (4), 491-496, 2005
972005
Modified Booth modulo 2/sup n/-1 multipliers
C Efstathiou, HT Vergos, D Nikolos
IEEE Transactions on Computers 53 (3), 370-374, 2004
912004
Area-time efficient modulo 2/sup n/-1 adder design
C Efstathiou, D Nikolos, J Kalamatianos
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1994
901994
Modulo 2/sup n//spl plusmn/1 adder design using select-prefix blocks
C Efstathiou, HT Vergos, D Nikolos
IEEE Transactions on Computers 52 (11), 1399-1406, 2003
832003
Systematic t-error correcting/all unidirectional error detecting codes
Nikolos, Gaitanis, Philokyprou
IEEE transactions on computers 100 (5), 394-402, 1986
711986
Low-power leading-zero counting and anticipation logic for high-speed floating point units
G Dimitrakopoulos, K Galanopoulos, C Mavrokefalidis, D Nikolos
IEEE transactions on very large scale integration (VLSI) systems 16 (7), 837-850, 2008
672008
Multilevel Huffman coding: An efficient test-data compression method for IP cores
X Kavousianos, E Kalligeros, D Nikolos
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007
642007
Efficient modular design of TSC checkers for m-out-of-2m codes
AM Paschalis, D Nikolos, C Halatsis
IEEE transactions on computers 37 (3), 301-309, 1988
551988
Test data compression based on variable-to-variable Huffman encoding with codeword reusability
X Kavousianos, E Kalligeros, D Nikolos
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008
512008
New architectures for modulo 2n-1 adders
G Dimitrakopoulos, DG Nikolos, HT Vergos, D Nikolos, C Efstathiou
2005 12th IEEE International Conference on Electronics, Circuits and Systems …, 2005
482005
Multilevel-Huffman test-data compression for IP cores with multiple scan chains
X Kavousianos, E Kalligeros, D Nikolos
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16 (7), 926-931, 2008
472008
Self-testing embedded two-rail checkers
D Nikolos
Journal of Electronic Testing 12, 69-79, 1998
451998
An efficient built-in self test method for robust path delay fault testing
I Voyiatzis, A Paschalis, D Nikolos, C Halatsis
Journal of Electronic Testing 8, 219-222, 1996
441996
Efficient design of totally self-checking checkers for all low-cost arithmetic codes
D Nikolos, AM Paschalis, G Philokyprou
IEEE transactions on computers 37 (7), 807-814, 1988
441988
Input test data compression based on the reuse of parts of dictionary entries: Static and dynamic approaches
P Sismanoglou, D Nikolos
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013
382013
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