ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining C Peltekis, D Filippas, G Dimitrakopoulos, C Nicopoulos, ... 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023 | 9 | 2023 |
Reduced-Precision Floating-Point Arithmetic in Systolic Arrays with Skewed Pipelines D Filippas, C Peltekis, G Dimitrakopoulos, C Nicopoulos 2023 IEEE 5th International Conference on Artificial Intelligence Circuits …, 2023 | 8 | 2023 |
FusedGCN: A systolic three-matrix multiplication architecture for graph convolutional networks C Peltekis, D Filippas, C Nicopoulos, G Dimitrakopoulos 2022 IEEE 33rd International Conference on Application-specific Systems …, 2022 | 8 | 2022 |
Low-power data streaming in systolic arrays with bus-invert coding and zero-value clock gating C Peltekis, D Filippas, G Dimitrakopoulos, C Nicopoulos 2023 12th International Conference on Modern Circuits and Systems …, 2023 | 3 | 2023 |
IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications V Titopoulos, K Alexandridis, C Peltekis, C Nicopoulos, ... 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2024 | 2 | 2024 |
Reusing Softmax Hardware Unit for GELU Computation in Transformers C Peltekis, K Alexandridis, G Dimitrakopoulos arXiv preprint arXiv:2402.10118, 2024 | 2 | 2024 |
Error Checking for Sparse Systolic Tensor Arrays C Peltekis, D Filippas, G Dimitrakopoulos arXiv preprint arXiv:2402.10850, 2024 | 1 | 2024 |
Exploiting data encoding and reordering for low-power streaming in systolic arrays C Peltekis, D Filippas, G Dimitrakopoulos, C Nicopoulos Microprocessors and Microsystems 102, 104938, 2023 | 1 | 2023 |
Optimizing Structured-Sparse Matrix Multiplication in RISC-V Vector Processors V Titopoulos, K Alexandridis, C Peltekis, C Nicopoulos, ... IEEE Transactions on Computers, 2025 | | 2025 |
GCN-ABFT: Low-Cost Online Error Checking for Graph Convolutional Networks C Peltekis, G Dimitrakopoulos IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | | 2024 |
Floating-Point Multiply-Add with Approximate Normalization for Low-Cost Matrix Engines K Alexandridis, C Peltekis, D Filippas, G Dimitrakopoulos 2024 31st IEEE International Conference on Electronics, Circuits and Systems …, 2024 | | 2024 |
A High-Level Synthesis Library for Synthesizing Efficient and Functional-Safe CNN Dataflow Accelerators D Filippas, C Peltekis, V Titopoulos, I Kansizoglou, G Sirakoulis, ... IEEE Access, 2024 | | 2024 |
DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity C Peltekis, V Titopoulos, C Nicopoulos, G Dimitrakopoulos IEEE Computer Architecture Letters, 2024 | | 2024 |
The Case for Asymmetric Systolic Array Floorplanning C Peltekis, D Filippas, G Dimitrakopoulos, C Nicopoulos arXiv preprint arXiv:2309.02969, 2023 | | 2023 |