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Hyungmin Cho
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ERSA: Error resilient system architecture for probabilistic applications
L Leem, H Cho, J Bau, QA Jacobson, S Mitra
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
3052010
Quantitative evaluation of soft error injection techniques for robust system design
H Cho, S Mirkhani, CY Cher, JA Abraham, S Mitra
Proceedings of the 50th Annual Design Automation Conference, 1-10, 2013
2912013
ERSA: Error resilient system architecture for probabilistic applications
H Cho, L Leem, S Mitra
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012
1472012
CLEAR: Cross-Layer Exploration for Architecting Resilience - Combining hardware and software techniques to tolerate soft errors in processor cores
E Cheng, S Mirkhani, LG Szafaryn, CY Cher, H Cho, K Skadron, MR Stan, ...
Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016
942016
ASIC-resistance of multi-hash proof-of-work mechanisms for blockchain consensus protocols
H Cho
IEEE Access 6, 66210-66222, 2018
872018
Gallager B decoder on noisy hardware
SMST Yazdi, H Cho, L Dolecek
IEEE Transactions on Communications 61 (5), 1660-1673, 2013
872013
Dynamic data scratchpad memory management for a memory subsystem with an MMU
H Cho, B Egger, J Lee, H Shin
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages …, 2007
692007
Fa3c: Fpga-accelerated deep reinforcement learning
H Cho, P Oh, J Park, W Jung, J Lee
Proceedings of the Twenty-Fourth International Conference on Architectural …, 2019
612019
The resilience wall: Cross-layer solution strategies
S Mitra, P Bose, E Cheng, CY Cher, H Cho, R Joshi, YM Kim, CR Lefurgy, ...
Proceedings of Technical Program-2014 International Symposium on VLSI …, 2014
442014
Impact of microarchitectural differences of RISC-V processor cores on soft error effects
H Cho
IEEE Access 6, 41302-41313, 2018
292018
Understanding soft errors in uncore components
H Cho, CY Cher, T Shepherd, S Mitra
Proceedings of the 52Nd Annual Design Automation Conference, 1-6, 2015
262015
Tolerating soft errors in processor cores using clear (cross-layer exploration for architecting resilience)
E Cheng, S Mirkhani, LG Szafaryn, CY Cher, H Cho, K Skadron, MR Stan, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
252017
Cross-layer error resilience for robust systems
L Leem, H Cho, HH Lee, YM Kim, Y Li, S Mitra
2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 177-180, 2010
242010
System-level effects of soft errors in uncore components
H Cho, E Cheng, T Shepherd, CY Cher, S Mitra
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
212017
Robust system design
S Mitra, H Cho, T Hong, YM Kim, HHK Lee, L Leem, Y Li, D Lin, ...
IPSJ Transactions on System LSI Design Methodology 4, 2-30, 2011
192011
Rethinking error injection for effective resilience
S Mirkhani, H Cho, S Mitra, JA Abraham
2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 390-393, 2014
172014
Correction to “ASIC-Resistance of Multi-Hash Proof-of-Work Mechanisms for Blockchain Consensus Protocols”
H Cho
IEEE Access 7, 25086-25086, 2019
122019
Probabilistic analysis of Gallager B faulty decoder
SMST Yazdi, H Cho, Y Sun, S Mitra, L Dolecek
2012 IEEE International Conference on Communications (ICC), 7019-7023, 2012
122012
FARNN: FPGA-GPU hybrid acceleration platform for recurrent neural networks
H Cho, J Lee, J Lee
IEEE Transactions on Parallel and Distributed Systems 33 (7), 1725-1738, 2021
102021
Minimal aliasing single-error-correction codes for dram reliability improvement
SI Pae, V Kozhikkottu, D Somasekar, W Wu, SG Ramasubramanian, ...
IEEE Access 9, 29862-29869, 2021
92021
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