| Effective Method for Simultaneous Gate Sizing and th Assignment Using Lagrangian Relaxation G Flach, T Reimann, G Posser, M Johann, R Reis IEEE transactions on computer-aided design of integrated circuits and …, 2014 | 60 | 2014 |
| Simultaneous gate sizing and vt assignment using fanin/fanout ratio and simulated annealing T Reimann, G Posser, G Flach, M Johann, R Reis 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2549-2552, 2013 | 24 | 2013 |
| Fast Lagrangian relaxation-based multithreaded gate sizing using simple timing calibrations A Sharma, D Chinnery, T Reimann, S Bhardwaj, C Chu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 20 | 2019 |
| Cell selection for high-performance designs in an industrial design flow TJ Reimann, CCN Sze, R Reis Proceedings of the 2016 on International Symposium on Physical Design, 65-72, 2016 | 14 | 2016 |
| Gate sizing and threshold voltage assignment for high performance microprocessor designs T Reimann, CCN Sze, R Reis The 20th Asia and South Pacific Design Automation Conference, 214-219, 2015 | 11 | 2015 |
| Simultaneous gate sizing and Vthassignment using Lagrangian Relaxation and delay sensitivities G Flach, T Reimann, G Posser, M Johann, R Reis 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 84-89, 2013 | 10 | 2013 |
| Challenges of cell selection algorithms in industrial high performance microprocessor designs T Reimann, CCN Sze, R Reis Integration 52, 347-354, 2016 | 9 | 2016 |
| Roteamento global de circuitos VLSI TJ Reimann | 6 | 2013 |
| On the accuracy of Elmore-based Delay Models GBV dos Santos, TJ Reimann, MO Johann, RAL Reis 2009 16th IEEE International Conference on Electronics, Circuits and Systems …, 2009 | 4 | 2009 |
| Cell selection to minimize power in high-performance industrial microprocessor designs TJ Reimann | 1 | 2016 |
| The fidelity property of the Elmore delay model in actual comparison of routing algorithms G Santos, T Reimann, M Johann, R Reis 2010 IEEE International Conference on Computer Design, 195-202, 2010 | 1 | 2010 |
| On the Elmore “Fidelity” under Nanoscale Technologies TJ Reimann, GBV Santos, RAL Reis 9th Microelectronics Students Forum-Chip on the Dunes, 2009 | 1 | 2009 |
| GR-PA: A cost pre-allocation model for global routing L Nunes, T Reimann, R Reis 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration …, 2013 | | 2013 |
| Routing algorithms performance in different routing scopes TJ Reimann, GBV Santos, RAL Reis 2010 17th IEEE International Conference on Electronics, Circuits and Systems …, 2010 | | 2010 |
| Modelo de Elmore Fitado Considerando Acoplamento Capacitivo TJ Reimann, GBV Santos Salão de Iniciação Científica (21.: 2009 out. 19-23: Porto Alegre, RS …, 2009 | | 2009 |
| Algoritmos de roteamento dirigidos a desempenho TJ Reimann | | 2009 |
| Resistências de driver típicas em nano-tecnologias CMOS TJ Reimann, GBV Santos Salão de Iniciação Científica (20.: 2008 out. 20-24: Porto Alegre, RS …, 2008 | | 2008 |
| Comparação de algoritmos para a geração de estruturas de roteamento dirigidas a desempenho TJ Reimann Salão de Iniciação Científica (19.: 2007: Porto Alegre, RS). Livro de …, 2007 | | 2007 |
| VLSI-SoC 2017 MSS Abdelrehim, J Azambuja, S Bodapati, M Brachmann, R Brum, ... | | |
| Negotiation-Based Global Routing for VLSI Circuits TJ Reimann, RAL Reis | | |
Ricardo Augusto da Luz ReisUFRGSVerified email at inf.ufrgs.br
