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Jason Anderson
Jason Anderson
Professor of Electrical and Computer Engineering, University of Toronto
Verified email at eecg.toronto.edu - Homepage
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Cited by
Year
LegUp: high-level synthesis for FPGA-based processor/accelerator systems
A Canis, J Choi, M Aldham, V Zhang, A Kammoona, JH Anderson, ...
Proceedings of the 19th ACM/SIGDA international symposium on Field …, 2011
8202011
A survey and evaluation of FPGA high-level synthesis tools
R Nane, VM Sima, C Pilato, J Choi, B Fort, A Canis, YT Chen, H Hsiao, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
7422015
LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems
A Canis, J Choi, M Aldham, V Zhang, A Kammoona, T Czajkowski, ...
ACM Transactions on Embedded Computing Systems (TECS) 13 (2), 1-27, 2013
4772013
VTR 7.0: Next generation architecture and CAD system for FPGAs
J Luu, J Goeders, M Wainberg, A Somerville, T Yu, K Nasartschuk, M Nasr, ...
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 (2), 1-30, 2014
4642014
The VTR project: architecture and CAD for FPGAs from verilog to routing
J Rose, J Luu, CW Yu, O Densmore, J Goeders, A Somerville, KB Kent, ...
Proceedings of the ACM/SIGDA international symposium on Field Programmable …, 2012
3662012
Active leakage power optimization for FPGAs
JH Anderson, FN Najm, T Tuan
ACM International Symposium on Field Programmable Gate Arrays, 33-41, 2004
2262004
A PUF design for secure FPGA-based embedded systems
JH Anderson
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 1-6, 2010
2012010
Power estimation techniques for FPGAs
JH Anderson, FN Najm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12 (10 …, 2004
1602004
CGRA-ME: A unified framework for CGRA modelling and exploration
SA Chin, N Sakamoto, A Rui, J Zhao, JH Kim, Y Hara-Azumi, J Anderson
2017 IEEE 28th international conference on application-specific systems …, 2017
1442017
Analytical placement for heterogeneous FPGAs
M Gort, JH Anderson
22nd international conference on field programmable logic and applications …, 2012
1112012
Modulo SDC scheduling with recurrence minimization in high-level synthesis
A Canis, SD Brown, JH Anderson
2014 24th International Conference on Field Programmable Logic and …, 2014
1052014
From software threads to parallel hardware in high-level synthesis for FPGAs
J Choi, S Brown, J Anderson
2013 International Conference on Field-Programmable Technology (FPT), 270-277, 2013
1052013
Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect
J Luu, JH Anderson, JS Rose
Proceedings of the 19th ACM/SIGDA international symposium on Field …, 2011
1032011
Method for application of network flow techniques under constraints
JH Anderson, SK Nag, G Stenz, S Dasasathyan
US Patent 7,143,380, 2006
952006
Power-aware technology mapping for LUT-based FPGAs
JH Anderson, FN Najm
2002 IEEE International Conference on Field-Programmable Technology, 2002 …, 2002
902002
An architecture-agnostic integer linear programming approach to CGRA mapping
SA Chin, JH Anderson
Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018
872018
Source-level debugging for FPGA high-level synthesis
N Calagar, SD Brown, JH Anderson
2014 24th international conference on field programmable logic and …, 2014
862014
Clock gating architectures for FPGA power reduction
S Huda, M Mallick, JH Anderson
2009 International Conference on Field Programmable Logic and Applications …, 2009
852009
From software to accelerators with LegUp high-level synthesis
A Canis, J Choi, B Fort, R Lian, Q Huang, N Calagar, M Gort, JJ Qin, ...
2013 International Conference on Compilers, Architecture and Synthesis for …, 2013
812013
Impact of cache architecture and interface on performance and area of FPGA-based processor/parallel-accelerator systems
J Choi, K Nam, A Canis, J Anderson, S Brown, T Czajkowski
2012 IEEE 20th International Symposium on Field-Programmable Custom …, 2012
802012
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Articles 1–20