| PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning L Song, X Qian, H Li, Y Chen 2017 IEEE International Symposium on High Performance Computer Architecture …, 2017 | 906 | 2017 |
| DPATCH: An Adversarial Patch Attack on Object Detectors X Liu, H Yang, Z Liu, L Song, H Li, Y Chen SafeAI 2019, AAAI's Workshop on Artificial Intelligence Safety, 2019 | 350 | 2019 |
| GraphR: Accelerating Graph Processing Using ReRAM L Song, Y Zhuo, X Qian, H Li, Y Chen 2018 IEEE International Symposium on High Performance Computer Architecture …, 2018 | 333 | 2018 |
| A Survey of Accelerator Architectures for Deep Neural Networks Y Chen, Y Xie, L Song, F Chen, T Tang Engineering 6 (3), 264-274, 2020 | 329 | 2020 |
| A spiking neuromorphic design with resistive crossbar C Liu, B Yan, C Yang, L Song, Z Li, B Liu, Y Chen, H Li, Q Wu, H Jiang Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 155 | 2015 |
| HyPar: Towards Hybrid Parallelism for Deep Learning Accelerator Array L Song, J Mao, Y Zhuo, X Qian, H Li, Y Chen 2019 IEEE International Symposium on High Performance Computer Architecture …, 2019 | 132 | 2019 |
| AtomLayer: A Universal ReRAM-Based CNN Accelerator with Atomic Layer Computation X Qiao, X Cao, H Yang, L Song, H Li 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), 103, 2018 | 118 | 2018 |
| MeDNN: A distributed mobile system with enhanced partition and deployment for large-scale DNNs J Mao, Z Yang, W Wen, C Wu, L Song, KW Nixon, X Chen, H Li, Y Chen 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 751-756, 2017 | 93 | 2017 |
| ReGAN: A pipelined ReRAM-based accelerator for generative adversarial networks F Chen, L Song, Y Chen 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 178-183, 2018 | 87 | 2018 |
| ReCom: An efficient resistive accelerator for compressed deep neural networks H Ji, L Song, L Jiang, HH Li, Y Chen 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 237-240, 2018 | 83 | 2018 |
| AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators L Song, F Chen, Y Zhuo, X Qian, H Li, Y Chen 2020 IEEE International Symposium on High Performance Computer Architecture …, 2020 | 67 | 2020 |
| GaaS-X: Graph Analytics Accelerator Supporting Sparse Data Representation using Crossbar Architectures N Challapalle, S Rampalli, L Song, N Chandramoorthy, K Swaminathan, ... 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture …, 2020 | 66 | 2020 |
| Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication L Song, Y Chi, A Sohrabizadeh, Y Choi, J Lau, J Cong Proceedings of the 2022 ACM/SIGDA International Symposium on Field …, 2022 | 65* | 2022 |
| Reram-based accelerator for deep learning B Li, L Song, F Chen, X Qian, Y Chen, HH Li 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 815-820, 2018 | 42 | 2018 |
| Serpens: A High Bandwidth Memory Based Accelerator for General-Purpose Sparse Matrix-Vector Multiplication L Song, Y Chi, L Guo, J Cong Proceedings of the 59th ACM/IEEE Design Automation Conference, 211-216, 2022 | 41* | 2022 |
| ZARA: A Novel Zero-free Dataflow Accelerator for Generative Adversarial Networks in 3D ReRAM F Chen, L Song, Y Chen 2019 56th ACM/IEEE Design Automation Conference (DAC), 1-6, 2019 | 38 | 2019 |
| SparseTrain: Exploiting Dataflow Sparsity for Efficient Convolutional Neural Networks Training P Dai, J Yang, X Ye, X Cheng, J Luo, L Song, Y Chen, W Zhao 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 31 | 2020 |
| Classification accuracy improvement for neuromorphic computing systems with one-level precision synapses Y Wang, W Wen, L Song, HH Li 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 776-781, 2017 | 27 | 2017 |
| PARC: A Processing-in-CAM Architecture for Genomic Long Read Pairwise Alignment Using ReRAM F Chen, L Song, Y Chen 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 175-180, 2020 | 22 | 2020 |
| NVSim-VXs an improved NVSim for variation aware STT-RAM simulation E Eken, L Song, I Bayram, C Xu, W Wen, Y Xie, Y Chen Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 20 | 2016 |
Yiran ChenJohn Cocke Distinguished Professor of Electrical and Computer Engineering, Duke UniversityVerified email at duke.edu
